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Electroplating bonding technology for chip interconnect, wafer level packaging and interconnect layer structures

No description available.
Identiferoai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/5325
Date01 December 2003
CreatorsJoung, Yeun-Ho
PublisherGeorgia Institute of Technology
Source SetsGeorgia Tech Electronic Thesis and Dissertation Archive
Languageen_US
Detected LanguageEnglish
TypeDissertation
Format27541007 bytes, application/pdf

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