Wong Wai-Chiu. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 94-101). / Abstracts in English and Chinese. / Abstract --- p.iii / Abstract in Chinese --- p.v / Acknowledgements --- p.vi / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.2 / Chapter 1.2 --- Progress on Interconnect-driven Floorplanning --- p.4 / Chapter 1.2.1 --- Congestion Optimization --- p.4 / Chapter 1.2.2 --- Buffer Insertion --- p.5 / Chapter 1.3 --- Contributions --- p.6 / Chapter 1.4 --- Organization of this Thesis --- p.7 / Chapter 2 --- "VLSI Circuit Design, Physical Design Cycle and Floorplanning" --- p.8 / Chapter 2.1 --- VLSI Circuit Design Cycle --- p.9 / Chapter 2.2 --- Physical Design Cycle --- p.10 / Chapter 2.2.1 --- Circuit Partitioning --- p.10 / Chapter 2.2.2 --- Floorplanning and Placement --- p.11 / Chapter 2.2.3 --- Routing --- p.12 / Chapter 2.2.4 --- Compaction --- p.12 / Chapter 2.3 --- Introduction to Floorplanning --- p.13 / Chapter 2.4 --- Types of Floorplan --- p.14 / Chapter 2.5 --- Simulated Annealing --- p.15 / Chapter 2.6 --- Floorplan Representation --- p.16 / Chapter 2.6.1 --- Polish Expression --- p.17 / Chapter 2.6.2 --- Sequence Pair --- p.18 / Chapter 2.6.3 --- Twin Binary Tree --- p.20 / Chapter 2.6.4 --- Comparisons between Different Floorplan Representations --- p.21 / Chapter 2.7 --- Chapter Summary --- p.22 / Chapter 3 --- Interconnect Optimization in Floorplanning --- p.24 / Chapter 3.1 --- Routing Congestion Optimization --- p.25 / Chapter 3.2 --- Buffer Planning --- p.26 / Chapter 3.3 --- Wire Sizing --- p.28 / Chapter 3.4 --- Simultaneous Wire Sizing and Buffer Planning --- p.30 / Chapter 3.5 --- Literature Review on Interconnect-driven Floorplanning --- p.31 / Chapter 3.5.1 --- Congestion Optimization --- p.31 / Chapter 3.5.2 --- Buffer Insertion --- p.36 / Chapter 3.6 --- Chapter Summary --- p.40 / Chapter 4 --- Floorplanning with Congestion Optimization and Buffer Block Planning --- p.41 / Chapter 4.1 --- Floorplanner Overview --- p.42 / Chapter 4.1.1 --- Grid Structure and Blocked Grids --- p.44 / Chapter 4.1.2 --- Buffer Block Planning --- p.44 / Chapter 4.2 --- Elmore Delay Model --- p.46 / Chapter 4.2.1 --- Wire Sizing --- p.47 / Chapter 4.2.2 --- Buffer Insertion --- p.48 / Chapter 4.2.3 --- Simultaneous Buffer Insertion and Wire Sizing --- p.49 / Chapter 4.3 --- Dynamic Programming Approach for Buffer Planning and Wire Sizing --- p.49 / Chapter 4.4 --- Implementation of the Dynamic Programming Approach --- p.51 / Chapter 4.5 --- Lookup Table Construction --- p.53 / Chapter 4.6 --- Congestion Model --- p.55 / Chapter 4.7 --- Cost Function --- p.56 / Chapter 4.8 --- Algorithm --- p.56 / Chapter 4.9 --- Experimental Results --- p.57 / Chapter 4.9.1 --- Experimental Results on Simultaneous Buffer Insertion and Wire Sizing --- p.57 / Chapter 4.9.2 --- Experimental Results of using the Table Lookup Approach --- p.58 / Chapter 4.10 --- Chapter Summary --- p.60 / Chapter 5 --- Floorplanning with Flexible Buffer Planning and Routability Op- timization --- p.63 / Chapter 5.1 --- Floorplanner Overview --- p.64 / Chapter 5.1.1 --- Constraints in Buffer Locations --- p.64 / Chapter 5.2 --- Congestion Estimation --- p.66 / Chapter 5.3 --- Buffer Location Computation --- p.67 / Chapter 5.3.1 --- Feasible Locations for Buffer Insertion --- p.67 / Chapter 5.3.2 --- Cost of Grids for Buffer Insertion --- p.69 / Chapter 5.3.3 --- Dynamic Programming Approach for Selecting Buffer Lo- cation of a Net --- p.70 / Chapter 5.3.4 --- An Example --- p.70 / Chapter 5.4 --- Congestion Model --- p.72 / Chapter 5.4.1 --- Net-count Congestion Model --- p.72 / Chapter 5.4.2 --- Grid-count Congestion Model --- p.74 / Chapter 5.5 --- Buffer Location Bounds --- p.75 / Chapter 5.6 --- Net Grouping --- p.77 / Chapter 5.7 --- Cost Function --- p.79 / Chapter 5.8 --- Algorithm . --- p.79 / Chapter 5.9 --- Experimental Results --- p.79 / Chapter 5.9.1 --- Net Grouping Factor --- p.80 / Chapter 5.9.2 --- Experimental Results of our Floorplanner --- p.80 / Chapter 5.9.3 --- Comparison on Different Congestion Models --- p.82 / Chapter 5.10 --- Chapter Summary --- p.83 / Chapter 6 --- Conclusion --- p.86 / Chapter 6.1 --- Discussion --- p.87 / Chapter 6.2 --- Improvements --- p.88 / Chapter 6.2.1 --- Net Grouping and Ordering --- p.88 / Chapter 6.2.2 --- Congestion Modelling --- p.89 / Appendix --- p.90 / Chapter A --- Overview on VLSI Technology --- p.91 / Chapter A.l --- Moore's Law and Trends in VLSI --- p.91 / Chapter A.2 --- Scaling --- p.93 / Bibliography --- p.101
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_323904 |
| Date | January 2002 |
| Contributors | Wong, Wai-Chiu., Chinese University of Hong Kong Graduate School. Division of Computer Science and Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English, Chinese |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, xiv, 101 leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
Page generated in 0.0015 seconds