Digital multipliers are an important part of most of digital computation systems, such as microcontrollers and microprocessors. Multiplication operation is a quite complex task, thus there is many different solution varying in area, speed and power consumption. An important notice is that multipliers often are a part of critical path of a system which makes them especially important for these factors. During last decade, power efficiency has become an important issue in digital design and a lot of design methods has been created and investigated to meet this subject. It is a known fact that most of power consumed by arithmetic circuit is dissipated by hazards and toggles (up to 75%), that do not bring any information to final result. The method of evaluating the amount of spurious switching and its effect on power dissipation is investigated here. This thesis aims to find a method to estimate switching characteristics and its effect on power dissipation of eight supplied multipliers given in form of HDL net-list with some software overhead. As switching generally stands for majority of power consumption in digital CMOS circuits, this effect gives also good indication of overall power dissipation. One of the difficulties in estimating average power and transition density is pattern dependency problem. The method based on Monte Carlo technique is used where an adequate accuracy is obtained within moderate time and resource usage. Three of investigated multipliers are net-lists created by using methodology developed in [21]. These are synthesized and laid out in the technology used by Atmel Norway. The amount of logical state changes is compared from pre- and post- synthesis net-lists. The technology mapped net-lists are also examined for power consumption to see the connection between switching and dynamic power dissipation. The fan-out delay model used to estimate total toggling gives a good approximation of circuit properties; it is however too simple to give a good estimate of spurious toggling inside the circuit and its effect on power consumption. The same estimation technique is used to investigate a DesignWare circuit (DW02) which is an industrial approach of building fast and power efficient multipliers. The results show that this is the most power effective solution among the examined circuits (45-47% less than the most power efficient circuit from [21]) It is also a solution with smallest amount of hazards during a multiplication operation (38-52%). A circuit generated by module generation software (ModGen) is also investigated. This solution is quite power efficient, it has however largest amount of power dissipated by the spurious toggling (62-68%). It is also noticed that transition density and what follows the power dissipation in strongly dependent on the process, temperature and voltage variation. In fact the higher temperature gives reduction in power consumption.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:ntnu-9919 |
| Date | January 2009 |
| Creators | Kalis, Jakub Jerzy |
| Publisher | Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, Institutt for elektronikk og telekommunikasjon |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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