A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a 12-bit multi-channel Wilkinson (single-slope integrating) Analog-to-Digital (ADC). This PWLL was designed and fabricated in a 0.5-um Silicon Germanium (SiGe) BiCMOS process. The PWLL architecture that is comprised of a phase detector, a charge-pump, and a pulse width modulator (PWM), is discussed along with the design details of the primary blocks. Simulation and silicon measurement data are shown that demonstrate a large improvement in the accuracy of the PVT-compensated ADC over the uncompensated ADC.
| Identifer | oai:union.ndltd.org:UTENN/oai:trace.tennessee.edu:utk_gradthes-1941 |
| Date | 01 May 2011 |
| Creators | Tham, Kevin Vun Kiat |
| Publisher | Trace: Tennessee Research and Creative Exchange |
| Source Sets | University of Tennessee Libraries |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Masters Theses |
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