Ping-Ki Tsang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaves 87-95). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Aims --- p.1 / Chapter 1.2 --- Contributions --- p.3 / Chapter 1.3 --- Overview of the Thesis --- p.4 / Chapter 2 --- Asynchronous Logic g --- p.6 / Chapter 2.1 --- Motivation --- p.6 / Chapter 2.2 --- Timing Models --- p.9 / Chapter 2.2.1 --- Fundamental-Mode Model --- p.9 / Chapter 2.2.2 --- Delay-Insensitive Model --- p.10 / Chapter 2.2.3 --- QDI and Speed-Independent Models --- p.11 / Chapter 2.3 --- Asynchronous Signalling Protocols --- p.12 / Chapter 2.3.1 --- 2-phase Handshaking Protocol --- p.12 / Chapter 2.3.2 --- 4-phase Handshaking Protocol --- p.13 / Chapter 2.4 --- Data Representations --- p.14 / Chapter 2.4.1 --- Dual Rail Coded Data --- p.15 / Chapter 2.4.2 --- Bundled Data --- p.15 / Chapter 2.5 --- Previous Asynchronous Processors --- p.16 / Chapter 2.6 --- Summary --- p.20 / Chapter 3 --- The MSL16 Architecture --- p.21 / Chapter 3.1 --- RISC Machines --- p.21 / Chapter 3.2 --- Stack Machines --- p.23 / Chapter 3.3 --- Forth and its Applications --- p.24 / Chapter 3.4 --- MSL16 --- p.26 / Chapter 3.4.1 --- Architecture --- p.28 / Chapter 3.4.2 --- Instruction Set --- p.30 / Chapter 3.4.3 --- The Datapath --- p.32 / Chapter 3.4.4 --- Interrupts and Exceptions --- p.33 / Chapter 3.4.5 --- Implementing Forth primitives --- p.34 / Chapter 3.4.6 --- Code Density Estimation --- p.34 / Chapter 3.5 --- Summary --- p.35 / Chapter 4 --- Design Methodology --- p.37 / Chapter 4.1 --- Basic Notation --- p.38 / Chapter 4.2 --- Specification of MSL16A --- p.39 / Chapter 4.3 --- Decomposition into Concurrent Processes --- p.41 / Chapter 4.4 --- Separation of Control and Datapath --- p.45 / Chapter 4.5 --- Handshaking Expansion --- p.45 / Chapter 4.5.1 --- 4-Phase Handshaking Protocol --- p.46 / Chapter 4.6 --- Production-rule Expansion --- p.47 / Chapter 4.7 --- Summary --- p.48 / Chapter 5 --- Implementation --- p.49 / Chapter 5.1 --- C-element --- p.49 / Chapter 5.2 --- Mutual Exclusion Elements --- p.51 / Chapter 5.3 --- Caltech Asynchronous Synthesis Tools --- p.53 / Chapter 5.4 --- Stack Design --- p.54 / Chapter 5.4.1 --- Eager Stack Control --- p.55 / Chapter 5.4.2 --- Lazy Stack Control --- p.56 / Chapter 5.4.3 --- Eager/Lazy Stack Datapath --- p.53 / Chapter 5.4.4 --- Pointer Stack Control --- p.61 / Chapter 5.4.5 --- Pointer Stack Datapath --- p.62 / Chapter 5.5 --- ALU Design --- p.62 / Chapter 5.5.1 --- The Addition Operation --- p.63 / Chapter 5.5.2 --- Zero-Checker --- p.64 / Chapter 5.6 --- Memory Interface and Tri-state Buffers --- p.64 / Chapter 5.7 --- MSL16A --- p.65 / Chapter 5.8 --- Summary --- p.66 / Chapter 6 --- Results --- p.67 / Chapter 6.1 --- FPGA based implementation of MSL16 --- p.67 / Chapter 6.2 --- MSL16A --- p.69 / Chapter 6.2.1 --- A Comparison of 3 Stack Designs --- p.69 / Chapter 6.2.2 --- Evaluation of the ALU --- p.73 / Chapter 6.2.3 --- Evaluation of MSL16A --- p.74 / Chapter 6.3 --- Summary --- p.81 / Chapter 7 --- Conclusions --- p.83 / Chapter 7.1 --- Future Work --- p.85 / Bibliography --- p.87 / Publications --- p.95
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_323248 |
| Date | January 2000 |
| Contributors | Tsang, Ping-Ki., Chinese University of Hong Kong Graduate School. Division of Computer Science and Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English, Chinese |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, xi, 95 leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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