This thesis presents the design of a Sensor Control Chip (SCC) developed to provide the required clock and bias signals for the Large Synoptic Survey Telescope’s CCD imagers. The circuit consists of current-summing DACs followed by trans-impedance operational amplifiers to control the rail voltages of the clock signals and bias voltages. The clocks are input to the SCC through LVDS receivers and converted internally to the required amplitude for driving the CCDs. The ASIC is designed to drive clock signals with 20-V adjustable output voltage swing and a maximum output current of 150 mA. The prototype chip has been fabricated in a 0.8-um BCD-SOI process, and is designed to operate down to 175K. Design techniques used in the ASIC will be presented, along with room temperature and operational temperature test results obtained from prototype chips. Test results have shown that the prototype chip is fully functional and agrees well with simulation results.
| Identifer | oai:union.ndltd.org:UTENN/oai:trace.tennessee.edu:utk_gradthes-1517 |
| Date | 01 December 2008 |
| Creators | Ning, Zuoliang |
| Publisher | Trace: Tennessee Research and Creative Exchange |
| Source Sets | University of Tennessee Libraries |
| Detected Language | English |
| Type | text |
| Source | Masters Theses |
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