Since the profitability of VLSI industries is related to yield, the IC manufacturer finds it highly desirable to be able to predict the yield by computer-aided methods. A key part in the procedure to obtain yield by computer simulation is to find the critical area of a layout. This thesis is primarily devoted to the calculations of critical area. There are two techniques to find the critical area. In the first technique, an analytic method was used to analyze the circuit geometry in order to find the critical area. In the second technique a Monte Carlo Method is used. A program using this Monte Carlo yield simulation (the main method used in this thesis) has been developed for determining critical area of the metal layer of a 4K random access memory. The analytic method is used in a supporting way. The thesis also proposes an easy method to process the vast amount of layout database. This method reduces the time consumed by Monte Carlo simulation.
| Identifer | oai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/278175 |
| Date | January 1992 |
| Creators | Lee, Li-Chyn, 1965- |
| Contributors | Parks, Harold G. |
| Publisher | The University of Arizona. |
| Source Sets | University of Arizona |
| Language | en_US |
| Detected Language | English |
| Type | text, Thesis-Reproduction (electronic) |
| Rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. |
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