Implementation of fault testing environment for embeded cores-based digital circuits is a challenging endeavor. The subject thesis aims developing techniques in design verification and test architecture utilizing well-known concepts of hardware and software co-design. There are available methods to ensure correct functionality, in both hardware and software, for embeded cores-based systems but one of the most used and acceptable approaches to realize this is through the use of design for testability. Specifically, applications of built-in self-test (BIST) methodology in testing embeded cores are considered in the thesis, with specific implementations being targeted towards ISCAS 85 combinational benchmark circuits. Experimental results provided in the thesis prove the validity and importance of the approaches proposed for the design verification and test based on hardware and software co-design concepts utilizing Altera MAX Plus II simulation environment.
| Identifer | oai:union.ndltd.org:uottawa.ca/oai:ruor.uottawa.ca:10393/26670 |
| Date | January 2004 |
| Creators | Jin, Liwu |
| Publisher | University of Ottawa (Canada) |
| Source Sets | Université d’Ottawa |
| Language | English |
| Detected Language | English |
| Type | Thesis |
| Format | 94 p. |
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