Today's computer and network communication systems rely on authenticated and
secure transmission of information, which requires computationally efficient and
low bandwidth cryptographic algorithms. Among these cryptographic algorithms
are the elliptic curve cryptosystems which use the arithmetic of finite fields. Furthermore,
the fields of characteristic two are preferred since they provide carry-free
arithmetic and at the same time a simple way to represent field elements on current
processor architectures.
Arithmetic in finite field is analogous to the arithmetic of integers. When
performing the multiplication operation, the finite field arithmetic uses reduction
modulo the generating polynomial. The generating polynomial is an irreducible
polynomial over GF(2), and the degree of this polynomial determines the size of
the field, thus the bit-lengths of the operands.
The fundamental arithmetic operations in finite fields are addition, multiplication,
and inversion operations. The sum of two field elements is computed very
easily. However, multiplication operation requires considerably more effort compared
to addition. On the other hand, the inversion of a field element requires much
more computational effort in terms of time and space. Therefore, we are mainly interested in obtaining implementations of field multiplication and inversion.
In this dissertation, we present several new bit-parallel hardware architectures with low space and time complexity. Furthermore, an analysis and refinement of the complexity of an existing hardware algorithm and a software method highly efficient and suitable for implementation on many 32-bit processor architectures are also described. / Graduation date: 1999
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/33927 |
| Date | 06 November 1998 |
| Creators | Sunar, Berk |
| Contributors | Koc, C. K. |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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