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VLSI implementation of low-error-floor multi-rate capacity-approaching low-density parity-check code decoder /

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (leaves 99-103).

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/76944274
Date January 2006
CreatorsYang, Lei,
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
TypeTheses
SourceConnect to this title online; UW restricted

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