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Vysokorychlostní přepínač dat / High-speed data switch

The master’s thesis is focused on desing high-speed ethernet switch based on circuit FPGA. The switch is able to divide one data stream, created from ethernet frames to the two data streams with half data flow.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:219860
Date January 2012
CreatorsToman, Jakub
ContributorsBobula, Marek, Kubíček, Michal
PublisherVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

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