Submitted by Automa??o e Estat?stica (sst@bczm.ufrn.br) on 2017-04-03T19:37:47Z
No. of bitstreams: 1
JonathanWanderleyDeMesquita_DISSERT.pdf: 4388700 bytes, checksum: c184689f12b45cb2f335af3627f06a1b (MD5) / Approved for entry into archive by Arlan Eloi Leite Silva (eloihistoriador@yahoo.com.br) on 2017-04-05T18:37:56Z (GMT) No. of bitstreams: 1
JonathanWanderleyDeMesquita_DISSERT.pdf: 4388700 bytes, checksum: c184689f12b45cb2f335af3627f06a1b (MD5) / Made available in DSpace on 2017-04-05T18:37:56Z (GMT). No. of bitstreams: 1
JonathanWanderleyDeMesquita_DISSERT.pdf: 4388700 bytes, checksum: c184689f12b45cb2f335af3627f06a1b (MD5)
Previous issue date: 2016-12-08 / Durante o projeto de arquiteturas multiprocessadas, a etapa de explora??o do espa?o de
projeto pode ser auxiliada por ferramentas que aceleram o processo. O projeto de uma
arquitetura com comunica??o baseada em rede-em-chip, usualmente considera topologias
regulares, e de car?ter gen?rico, desconsiderando uma eventual irregularidade no padr?o
de comunica??o entre os elementos interligados. Projetos heterog?neos necessitam de solu??es
de comunica??o ad-hoc, onde a explora??o manual do espa?o de projeto se torna
invi?vel, dada a sua complexidade. O presente trabalho prop?e uma rede em chip de topologia
irregular, capaz de ter bons desempenhos (pr?ximo ao desempenho de uma rede
conectada segundo o grafo da aplica??o), por meio de um processo de comunica??o baseado
em tabelas de roteamento. Tamb?m, uma ferramenta de explora??o em alto n?vel
utilizando Algoritmo Gen?tico, capaz de encontrar redes UTNoCs com n?mero reduzido
de conex?es, e auxiliando em decis?es de projetos destas redes. Resultados obtidos corroboram
o trabalho, obtendo redes UTNoCs com desempenhos pr?ximos aos de redes conectadas segundo os grafos de suas aplica??es, e com redu??o no n?mero de conex?es de at? 54%, representando uma redu??o significativa de ?rea e consumo de energia. / During the design of multiprocessor architectures, the design space exploration step may
be aided by tools that assist and accelerate this process. The project of architectures
whose communications are based on Networks-on-Chip (NoCs), usually relies on regular
topologies, disregarding a possible irregularity in the communication pattern between the
interconnected elements. The present work proposes an irregular topology chip network,
capable of having good performance (close to the performance of a network connected
according to the application graph), through a communication process based on routing
tables. The work proposes also a high-level exploration tool using Genetic Algorithm, able
to find UTNoC networks with reduced number of connections, and assisting in the design
decisions of these networks. The obtained Results show that it?s possible to obtain UTNoC
networks with performances close to the performance of networks connected according to
the graphs of their applications, and with a reduction in the number of connections of up
to 54%, representing a significant reduction of area and energy consumption.
| Identifer | oai:union.ndltd.org:IBICT/oai:repositorio.ufrn.br:123456789/22558 |
| Date | 08 December 2016 |
| Creators | Mesquita, Jonathan Wanderley de |
| Contributors | 58534296049, http://lattes.cnpq.br/6374279398246756, Pereira, M?nica Magalh?es, 00990410498, http://lattes.cnpq.br/5777010848661813, Zeferino, Cesar Albenes, 65254856068, http://lattes.cnpq.br/9888386354516064, Kreutz, M?rcio Eduardo |
| Publisher | PROGRAMA DE P?S-GRADUA??O EM SISTEMAS E COMPUTA??O, UFRN, Brasil |
| Source Sets | IBICT Brazilian ETDs |
| Language | Portuguese |
| Detected Language | English |
| Type | info:eu-repo/semantics/publishedVersion, info:eu-repo/semantics/masterThesis |
| Source | reponame:Repositório Institucional da UFRN, instname:Universidade Federal do Rio Grande do Norte, instacron:UFRN |
| Rights | info:eu-repo/semantics/openAccess |
Page generated in 0.0113 seconds