Fixed Broadband Wireless Access (FBWA) is a technology aimed at providing high-speed wireless Internet access, over a wide area, from devices such as personal computers and laptops. FBWA channels are defined in the range of 1-20 MHz which makes the RF front end (RFE) design extremely challenging. In its pursuit to standardize the Broadband Wireless Access (BWA) technologies, IEEE working group 802.16 for Broadband Wireless Access has released the fixed BWA standard IEEE 802.16 – 2004 in 2004. This standard is further backed by a consortium, of leading wireless vendors, chip manufacturers and service providers, officially known as Wireless Interoperability for Microwave Access (WiMAX).
In general, any wireless base station (BS), supporting a number of contiguous Frequency Division Multiplexed (FDM) channels has to incorporate an RF front end (RFE) for each RF channel. The precise job of the RFE is to filter the desired channel from a group of RF channels, digitize it and present it to the subsequent baseband system at the proper sampling rate. The system essentially has a bandpass filter (BPF) tuned to the channel of interest followed by a multiplier which brings the channel to a suitable intermediate frequency (IF). The IF output is digitized by an ADC and then brought to the baseband by an appropriate digital multiplier. The baseband samples, thus generated, are at the ADC sampling rate which is significantly higher than the target sampling rate, which is defined by the wireless protocol in use. As a result a sampling rate conversion (SRC) is performed on these baseband samples to bring the channel back to the target sampling rate. Since the input sampling rate need not be an integer multiple of the target sampling rate, Fractional SRC (FSRC) is required in most of the cases. Instead of using a separate ADC and IF section for each individual channels, most systems use a common IF section, followed by a wideband ADC, which operates over a wide frequency band containing a group of contiguous FDM channels. In this case a channelizer is employed to digitally extract the individual channels from the digital IF samples. We formally call this system a receiver channelizer. Such an implementation presents considerable challenge in terms of the computational requirement and of course the cost of the BS. The computational complexity further goes up for FBWA system where channel bandwidth is in the order of several MHz. Though such a system has been analyzed for narrow band wireless systems like GSM, to the best of our knowledge no analysis seems to have been carried out for a wideband system such as WiMAX.
In this work, we focus on design of a receiver channelizer for WiMAX BS, which can simultaneously extract a group of contiguous FDM RF channels supported by the BS. The main goal is to obtain a simple, low cost channelizer architecture, which can be implemented in an FPGA. There are a number of techniques available in the literature, from Direct Digital Conversion to Polyphase FFT Filter Banks (PFFB), which can do the job of channelization. But each of them operates with certain constraints and, as a result, suits best to a particular application. Further all of these techniques are generic in nature, in the sense that their structure is independent of any particular standard. With regard to computational requirement of these techniques, PFFB is the best, with respect to the number of complex multiplications required for its implementation. But it needs two very stringent conditions to be satisfied, viz. the number of channels to be extracted is equal to the decimation factor and the sampling rate is a power of 2 times baseband bandwidth. Clearly these conditions may not be satisfied by different wireless communication standards, and in fact, this is not satisfied by the WiMAX standard.
This gives us the motivation to analyze the receiver channelizer for WiMAX BS and to find an efficient and low cost architecture of the same. We demonstrate that even though the conditions required by PFFB are not satisfied by the WiMAX standard, we can modify the overall architecture to include the PFFB structure. This is achieved by dividing the receiver channelizer into two blocks. The first block uses the PFFB structure to separate the desired number of channels from the input samples. This process also achieves an integer SRC by a factor that is equal to the number of channels being extracted. This block generates baseband outputs whose sampling rates are related to their target sampling rate by a fractional multiplication factor. In order to bring the channels to their target sampling rate, each output from the PFFB block is fed to a FSRC block, whose job is to use an efficient FSRC algorithm to generate the samples at the target sampling rate. We show that the computational complexity, as compared to the direct implementation, is reduced by a factor, which is approximately equal to the square of the number of channels.
After mathematically formulating the receiver channelizer for WiMAX BS, we perform the simulation of the system using a software tool. There are two basic motives behind the simulation of the system which has a mathematical model. Firstly, the software simulation will give an idea whether the designed system is physically realizable. Secondly, this will help in designing the logic for different blocks of the system. Once these individual blocks are simulated and tested, they can be smoothly ported onto an FPGA.
For simulation purpose, we parameterize the receiver channelizer in such a way that it can be reconfigured for different ADC sampling rates and IF frequencies, by changing the input clock rate. The system is also reconfigurable in terms of the supported channel bandwidth. This is achieved by storing all the filter coefficients pertaining to each channel type, and loading the required coefficients into the computational engine. Using this methodology we simulate the system for three different IF frequencies (and the corresponding ADC sampling rates) and three different channel types, thus leading to nine different system configurations. The simulation results are in agreement with the mathematical model of the system.
Further, we also discuss some important implementation issues for the reconfigurable receiver channelizer. We estimate the memory requirement for implementing the system in an FPGA. The implementation delay is estimated in terms of number of samples.
The thesis is organized in five chapters. Chapter 1 gives a brief introduction about the WiMAX system and different existing channelization architecture followed by the outline of the proposed receiver channelizer. In chapter 2, we analyze the proposed receiver channelizer for WiMAX BS and evaluate its computational requirements. Chapter 3 outlines the procedure to generate the WiMAX test signal and specification of the all the filters used in the system. It also lists the simulation parameters and records the results of the simulation. Chapter 4 presents the details of a possible FPGA implementation. We present the concluding remarks and future research directions in the final chapter.
| Identifer | oai:union.ndltd.org:IISc/oai:etd.ncsi.iisc.ernet.in:2005/614 |
| Date | 02 1900 |
| Creators | Hoda, Nazmul |
| Contributors | Ramakrishnan, K R |
| Source Sets | India Institute of Science |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Relation | G21068 |
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