User-programmable, integrated circuits (ICs) e.g. Field Programmable Gate Arrays (FPGAs) are increasingly popular for embedded, high-performance data exploitation. They combine the parallelization capability and processing power of application specific integrated circuits (ASICs) with the exibility, scalability and adaptability of software-based processing solutions. FPGAs provide powerful processing resources due to an optimal adaptation to the target application and a well-balanced ratio of performance, efficiency and parallelization.
One drawback of FPGA-based data exploitation is the limited memory capacity of reconfigurable integrated circuits. Large-scale Digital Signal Processor (DSP) FPGAs provide approximately 4MB on-board random access memory (RAM) which is not sufficient to buffer the broadband sensor and result data. Hence, additional external memory is connected to the FPGA to increase on-board storage capacities.
External memory devices like double data rate three synchronous dynamic random access memories (DDR3-SDRAM) provide very fast and wide bandwidth interfaces that represent a bottleneck when used in highly parallelized processing architectures. Independent processing modules are demanding concurrent read and write access.
Within the master thesis, a concept for the integration of an external DDR3- SDRAM into an FPGA-based parallelized processing architecture is developed and implemented. The solution realizes time division multiple access (TDMA) to the external memory and virtual, low-latency memory extension to the on-board buffer capabilities. The integration of the external RAM does not change the way how on-board buffers are used (control, data-fow).
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:20869 |
| Date | 08 February 2018 |
| Creators | Lodaya, Bhaveen |
| Contributors | Blokzyl, Stephan, Hardt, Wolfram, Technische Universität Chemnitz |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | doc-type:masterThesis, info:eu-repo/semantics/masterThesis, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
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