Highly dense Multiple-Input Multiple-Output (MIMO) radars provide robust detection at a high angular resolution in automotive applications. However, these systems require extensive parallel processing, higher off-chip communication data rates, and higher power consumption as a result of denser arrays to tackle. In this work, concepts, algorithms and circuits for the first-in-literature System-on-Chip (SoC) performing on-chip 5D localization of targets are researched and developed. The targeted system features a scalable homogeneous architecture for fully integrated signal processing of Frequency Modulated Continuous Wave (FMCW) signals and near-sensor smart capabilities for the identification of critical targets (e.g., pedestrians) in an automotive context. To achieve this functionality at a low-power budget, the interconnection of locally constrained processing nodes each with low-area and low-power accelerators operating at low frequencies is developed. The design of efficient algorithms, data flow, and cognitive concepts is also researched and presented to provide an unconventional holistic co-design approach. As a result of the research carried out in this thesis, a 12-ADC multi-core Digital Signal Processor (DSP) in 22FDX GLOBALFOUNDRIES (GF) using Adaptive Body Biasing (ABB) at 0.6V to enable smart on-chip classification with 25 processing elements (PEs) is proposed, providing a low power consumption of only 52.6mW that is at least 90x lower than the state-of-the-art commercial MIMO Radar DSPs.:Abstract
Zusammenfassung
List of Figures
List of Tables
Nomenclature
1. Introduction
1.1. Introduction
1.2. Motivation
1.3. Aims and Objectives
1.4. Contributions
1.5. Publications
1.6. Thesis Outline
2. Signal Processing for 5D Radars
2.1. Signal Processing Overview
2.2. Velocity Disambiguation Proposals for MIMO Radars
2.3. Cognitive Principles
2.4. Proposed Clustering for Constrained Processors
2.5. Target Classification
2.6. Summary of the Proposed Contributions
3. Hardware for 5D Radars: A Prototype Implementation
3.1. Multiprocessor Systems-on-Chip
3.2. FFT Acceleration
3.3. Silicon Implementation
3.4. Proposed Testchip
3.5. Proposed Implementation of the Processing Stages
3.6. Summary of Contributions
4. Conclusion and Outlook
4.1. Summary
4.2. Applications
4.3. Further Work
4.4. Conclusion
A. Appendix
A.1. FMCW Equations
A.2. Dataset for Velocity Disambiguation
A.3. Dataset for Machine Learning
A.4. Dataset for Cognitive Radar Mode
A.5. Reliability Proof for the Ambiguity Detector
A.6. Measurement Setup
A.7. EDA Tools Used in this Work
Publications
Bibliography / Hochdichte MIMO-Radar-Systeme bieten robuste Detektion mit hoher Winkelauflösung in Automobilanwendungen. Diese Systeme erfordern jedoch aufgrund dichterer Arrays umfangreiche parallele Verarbeitung, höhere Datenraten für die Off-Chip-Kommunikation und einen höheren Stromverbrauch. In dieser Arbeit werden Konzepte, Algorithmen und Schaltungen für den erstmaligen SoC-Ansatz zur On-Chip-Lokalisierung von Zielen in fünf Dimensionen untersucht und entwickelt. Das angestrebte System zeichnet sich durch eine skalierbare homogene Architektur für die vollständig integrierte Signalverarbeitung von FMCW-Signalen aus sowie durch intelligente Fähigkeiten in der Nähe des Sensors zur Identifizierung kritischer Ziele (z. B. Fußgänger) im automobilen Kontext. Um diese Funktionalität bei geringem Energieverbrauch zu erreichen, wird die Verbindung von lokal begrenzten Verarbeitungsknoten mit niedrigflächigen und energieeffizienten Beschleunigern entwickelt, die bei niedrigen Frequenzen arbeiten. Des Weiteren werden effiziente Algorithmen, Datenflüsse und kognitive Konzepte erforscht und präsentiert, um einen unkonventionellen ganzheitlichen Co-Design-Ansatz zu bieten. Als Ergebnis der in dieser Arbeit durchgeführten Forschung wird ein 12-ADC-Multi-Core-DSP in 22FDX GF mit ABB bei 0,6V vorgeschlagen, um eine intelligente On-Chip-Klassifizierung mit 25 Verarbeitungselementen (PEs) zu ermöglichen. Dieser Prozessor weist einen geringen Stromverbrauch von lediglich 52,6mW auf, der mindestens 90-mal niedriger ist als bei den modernsten kommerziellen MIMO-Radar-DSPs.:Abstract
Zusammenfassung
List of Figures
List of Tables
Nomenclature
1. Introduction
1.1. Introduction
1.2. Motivation
1.3. Aims and Objectives
1.4. Contributions
1.5. Publications
1.6. Thesis Outline
2. Signal Processing for 5D Radars
2.1. Signal Processing Overview
2.2. Velocity Disambiguation Proposals for MIMO Radars
2.3. Cognitive Principles
2.4. Proposed Clustering for Constrained Processors
2.5. Target Classification
2.6. Summary of the Proposed Contributions
3. Hardware for 5D Radars: A Prototype Implementation
3.1. Multiprocessor Systems-on-Chip
3.2. FFT Acceleration
3.3. Silicon Implementation
3.4. Proposed Testchip
3.5. Proposed Implementation of the Processing Stages
3.6. Summary of Contributions
4. Conclusion and Outlook
4.1. Summary
4.2. Applications
4.3. Further Work
4.4. Conclusion
A. Appendix
A.1. FMCW Equations
A.2. Dataset for Velocity Disambiguation
A.3. Dataset for Machine Learning
A.4. Dataset for Cognitive Radar Mode
A.5. Reliability Proof for the Ambiguity Detector
A.6. Measurement Setup
A.7. EDA Tools Used in this Work
Publications
Bibliography
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:94103 |
| Date | 22 October 2024 |
| Creators | Gonzalez Diaz, Hector A. |
| Contributors | Mayr, Christian, Baker, Christopher, Andres, Björn, Technische Universität Dresden |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | info:eu-repo/semantics/publishedVersion, doc-type:doctoralThesis, info:eu-repo/semantics/doctoralThesis, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | 10.1109/ISCAS51556.2021.9401547, 10.1109/RWS50353.2021.9360348, 10.1109/ISCAS45731.2020.9180728, 10.1109/EBCCSP51266.2020.9291357, 10.1109/EMBC.2019.8857248, 10.1109/RADAR41533.2019.171412, 10.1109/ACCESS.2020.3012900, 10.1109/TBCAS.2021.3089132, 10.1049/rsn2.12063, 10.1109/RadarConf2248738.2022.9764207, 10.1109/TC.2022.3162708, 10.1109/CICC57935.2023.10121258, 10.23919/IRS57608.2023.10172424, 10.1109/ISCAS58744.2024.10558386, 10.3389/fnins.2022.851774, info:eu-repo/grantAgreement/Federal Ministry of Education and Research of Germany/Souverän. Digital. Vernetzt/16KISK001K//Joint Project 6G-life/6G-life |
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