Indiana University-Purdue University Indianapolis (IUPUI) / This thesis presents a Field Programmable Gate Array (FPGA) based embedded
system which is used to achieve high speed segmentation of 3D images. Segmenta-
tion is performed using Expectation-Maximization with Maximization of Posterior
Marginals (EM/MPM) Bayesian algorithm. In this system, the embedded processor
controls a custom circuit which performs the MPM and portions of the EM algorithm.
The embedded processor completes the EM algorithm and also controls image data
transmission between host computer and on-board memory. The whole system has
been implemented on Xilinx Virtex 6 FPGA and achieved over 100 times improvement
compared to standard desktop computing hardware.
| Identifer | oai:union.ndltd.org:IUPUI/oai:scholarworks.iupui.edu:1805/2633 |
| Date | 08 1900 |
| Creators | Liu, Chao |
| Contributors | Christopher, Lauren, Rizkalla, Maher E., Salama, Paul |
| Source Sets | Indiana University-Purdue University Indianapolis |
| Language | en_US |
| Detected Language | English |
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