International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Phase-locked loop (PLL) frequency synthesizers used for high-speed data transmission must rapidly
hop and lock to new frequencies. The fundamental problem is that the settling time depends
inversely on the loop bandwidth, and increasing the bandwidth causes unwanted noise interference
and stability problems for the circuit. We demonstrate the feasibility of replacing the analog
integrator in the PLL with a digital integrator. This circuit has advantages of increased hopping
speed, ability to compensate for temperature drift and system stability. PLL lock-in was
demonstrated in a prototype circuit designed and built with both discrete components and with a
programmable logic device.
| Identifer | oai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/605595 |
| Date | 10 1900 |
| Creators | Holtzman, Melinda, Johnson, Bruce, Lautzenhiser, Lloyd |
| Contributors | University of Nevada, Emhiser Research, Incorporated |
| Publisher | International Foundation for Telemetering |
| Source Sets | University of Arizona |
| Language | en_US |
| Detected Language | English |
| Type | text, Proceedings |
| Rights | Copyright © International Foundation for Telemetering |
| Relation | http://www.telemetry.org/ |
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