This thesis includes two topics. The first topic is a ZigBee transceiver used in 2.45 GHz
band design. The second topic is a 2K/4K/8K multimode fast Fourier transformation ( FFT ) for
DVB-H demodulators.
The first topic includes simulations and hardware design. The chip is a physical layer
design compliant with IEEE Std 802.15.4 standard, including a transmitter and a receiver for
2.45 GHz band. The measurement of the maximum power on silicon is about 731 £gW at 8
MHz. It is proved to be compliant with the low power consumption requirement specified by the
standard.
The second topic includes simulations and hardware design of an FFT for DVB-H
demodulators. This processor is based on a pipeline architecture with radix-2, radix-22 and
radix-23 computation element. We propose one sharing butterfly architecture to be used in the
variable length FFT processor.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0711107-162649 |
| Date | 11 July 2007 |
| Creators | Lee, Lung-hsuan |
| Contributors | Chua-Chin Wang, Chih-Peng Li, Ju-Ya Chen, Sying-Jyan Wang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0711107-162649 |
| Rights | not_available, Copyright information available at source archive |
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