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A DIGITAL INTEGRATOR FOR AN S-BAND HIGH-SPEED FREQUENCY-HOPPING PHASE-LOCKED LOOP

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Phase-locked loop (PLL) frequency synthesizers used for high-speed data transmission must rapidly
hop and lock to new frequencies. The fundamental problem is that the settling time depends
inversely on the loop bandwidth, and increasing the bandwidth causes unwanted noise interference
and stability problems for the circuit. We demonstrate the feasibility of replacing the analog
integrator in the PLL with a digital integrator. This circuit has advantages of increased hopping
speed, ability to compensate for temperature drift and system stability. PLL lock-in was
demonstrated in a prototype circuit designed and built with both discrete components and with a
programmable logic device.

Identiferoai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/605595
Date10 1900
CreatorsHoltzman, Melinda, Johnson, Bruce, Lautzenhiser, Lloyd
ContributorsUniversity of Nevada, Emhiser Research, Incorporated
PublisherInternational Foundation for Telemetering
Source SetsUniversity of Arizona
Languageen_US
Detected LanguageEnglish
Typetext, Proceedings
RightsCopyright © International Foundation for Telemetering
Relationhttp://www.telemetry.org/

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