With the progress in VLSI technology, the external environment makes it easier for the interference affected the operation of microcontroller. The design of the recently microcontroller, not only the pursuit of speed and performance, also began the study of the various fault-tolerant technology to enhance the reliability and safety. This thesis, being designed for the Fault-tolerant microcontroller according market, presents a Robust Micro-Control Unit : RMCU for dual core architecture of ARM9 ISA.
The RMCU provides two operation modes: synchronize mode and Processor test mode for fault-tolerant mechanism. In synchronize mode, both processors are executing the same program concurrently. The results generated by processors are compared, and every mismatch indicates a transient fault in one of the two processors. When the transient fault occurred, the two processors will use Instruction retry mechanism, recover system operation. If the same address's errors larger than the number of settings are considered permanent fault, processors will be held, and entered the processor test mode for processor functional test. In accordance with the test results to close the wrong processor and operating system back to normal. This approach to solve the traditional dual-core processor fault-tolerant architecture that can not be fixed to permanent-fault restrictions.
In addition to the design of fault-tolerance mechanism, for the upgrading of software and hardware development and validation of this paper design of the RMCU debug platform. RMCU debug platform including JTAG-based OCD (On-Chip Debugging) unit, and debug interface program. In addition to providing read and write registers and memory, set Breakpoint, Watchpoint and single-step but also take the initiative to increase the external interrupt inserted to provide a more effective ISR (Interrupt Service Routine) debug. In the last of the thesis, we use the FPGA Implementation of the RMCU fault-tolerant mechanisms and debug platform. After simulation and testing, the results prove the feasibility of RMCU.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0819108-220413 |
| Date | 19 August 2008 |
| Creators | Shih, Wei-Chih |
| Contributors | Ing-Jer Huang, Jih-Ching Chiu, Chung-Ping Chung |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0819108-220413 |
| Rights | not_available, Copyright information available at source archive |
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