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Performance evaluation of fault tolerant methodologies for network on chip architecture

Thesis (M.S. in electrical engineering)--Washington State University, August 2007. / Includes bibliographical references (p. 57-59).

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/166886006
Date January 2007
CreatorsZhu, Haibo,
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceOnline access for everyone

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