An efficient architecture for detection of multiple bit upsets in processor register files

Description

Thesis (M.S.)--Rutgers University, 2009. / "Graduate Program in Electrical and Computer Engineering." Includes bibliographical references (p. 60-62).

Links & Downloads

1. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000051428

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Additional Fields

Identifer	oai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/501387740
Date	January 2009
Creators	Yueh, Wen,
Source Sets	OCLC
Language	English
Detected Language	English