A 2T2C ferroelectric memory cell consisting of a select transistor, a read transistor and two ferroelectric capacitors that can be operated either in FeRAM mode or in memristive ferroelectric tunnel junction mode is proposed. The two memory devices can be programmed individually. By performing a combined readout operation, the two stored bits of the memory cells can be combined to perform in-memory logic operation. Moreover, additional input logic signals that are applied as external readout voltage pulses can be used to perform logic operation together with the stored logic states of the ferroelectric capacitors. Electrical characterization results of the logic-in-memory (LiM) functionality is presented.
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:77006 |
| Date | 17 December 2021 |
| Creators | Ravsher, Taras, Mulaosmanovic, Halid, Breyer, Evelyn T., Havel, Viktor, Mikolajick, Thomas, Slesazeck, Stefan |
| Publisher | IEEE |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English, German |
| Detected Language | English |
| Type | info:eu-repo/semantics/acceptedVersion, doc-type:conferenceObject, info:eu-repo/semantics/conferenceObject, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | 978-1-72810-996-1, 10.1109/ICECS46596.2019.8965155, info:eu-repo/grantAgreement/European Commission/Horizon 2020/780302//Energy - Efficient Embedded Non-volatile Memory Logic based on Ferroelectric Hf(Zr)O2/3eFERRO |
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