FPGA clock frequencies are slow enough that only a fraction of the interconnect’s
bandwidth is used. By exploiting this bandwidth, the transfer of large amounts of
data can be greatly accelerated. Alternatively, it may also be possible to save area
on fixed-bandwidth links by using on-chip serial signaling. For datapath-intensive
designs which operate on words instead of bits, this can reduce wiring congestion
as well. This thesis proposes relatively simple circuit-level modifications to FPGA
interconnect to enable high-bandwidth communication. High-level area estimates
indicate a potential interconnect area savings of 10 to 60% when serial links are used.
Two interconnect pipelining techniques, wave pipelining and surfing, are adapted
to FPGAs and compared against each other and against regular FPGA interconnect
in terms of throughput, reliability, area, power, and latency. Source-synchronous
signaling is used to achieve high data rates with simple receiver design. Statistical
models for high-frequency power supply noise are developed and used to estimate the
probability of error of wave pipelined and surfing links as a function of link length
and operating speed. Surfing is generally found to be more reliable and less sensitive
to noise than wave pipelining. Simulation results in a 65nm process demonstrate a
throughput of 3Gbps per wire across a 50-stage, 25mm link.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:BVAU./2767 |
| Date | 05 1900 |
| Creators | Teehan, Paul Leonard |
| Publisher | University of British Columbia |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | English |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Format | 4713151 bytes, application/pdf |
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