In modern high-speed digital circuits, the space of the traditional single-layered or double-layered circuit board is not enough, therefore multi-layered circuit and stacked distribution technology are widely applied to many applications. The signal via is a vertical interconnection structure to communicate different signal layers, which will be seriously interfere with the simultaneous switching noise by via through the parallel plate cavity that consists of power and ground plane. It is an important issue to minimize the influence from noise.
In multi-layered printed circuit boards, shorting vias are usually utilized to interconnect the planes with the same voltage level. The major theme of this thesis is the placement of shorting vias affecting plane cavity mode. And we propose a design rule of the shorting vias to significantly decrease the simultaneous switching noise and improve the power integrity of multi-layered circuit board.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0719111-224316 |
| Date | 19 July 2011 |
| Creators | Yu, Sheng-yueh |
| Contributors | Ken-huang Lin, Chih-wen Kuo, Chie-in Lee |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719111-224316 |
| Rights | not_available, Copyright information available at source archive |
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