Thesis (MScEng)--Stellenbosch University, 2005. / ENGLISH ABSTRACT: This thesis investigates the possible use of NAND flash memory for a mass memory unit
on a micro-satellite. The investigation begins with an analysis of NAND flash memory devices
including the complexity of the internal circuitry and the occurrence of bad memory
sections (bad blocks). Design specifications are produced and various design architectures
are discussed and evaluated. Subsequently, a four bus serial access architecture using 16-
bit NAND flash devices was chosen to be developed further.
A VHDL design was created in order to realise the intended system functionality. The
main functions of the design include a sustained write data rate of 24 MB/s, bad block
management, multiple image storing, error checking and correction, defective device handling
and reading while writing. The design was simulated extensively using NAND flash
simulation models.
Finally, a demonstration test board was designed and produced. This board includes an
FPGA and an array of 16 8-bit NAND flash devices. The board was tested sucessfully
and a write data rate of 12 MB/s was achieved along with all the other main functions. / AFRIKAANSE OPSOMMING: Hierdie tesis ondersoek die moontlike gebruik van NAND flash tegnologie as die geheue
eenheid van ’n mikrosatelliet. As ’n beginpunt word NAND flash tegnologie ondersoek
in terme van die kompleksiteit van interne stroombane en die voorkoms van defektiewe
geheuesegmente. Daarna word ontwerpspesifikasies voortgebring en verskillende
ontwerpsmoontlikhede met mekaar vergelyk. Vanuit hierdie oorwegings is daar besluit
om die oplossing te implementeer met ’n vier-bus seri¨ele struktuur bestaande uit 16-bis
NAND flash toestelle.
Om die ontwerpspesifikasies te realiseer, is ’n VHDL stelsel geskep. Die belangrikste
funksies van hierdie stelsel is ’n konstante skryftempo van 24 MB/s, die bestuur van
defektiewe geheuesegmente, die stoor van meer as een beeld, foutopsporing en -herstel,
optimale werking in die geval van defektiewe geheuetoestelle en laastens, die gelyktydige
lees en skryf van data. Die stelsel is breedvoerig getoets met NAND flash simulasiemodelle.
Ten slotte is ’n fisiese demonstrasiebord, bestaande uit ’n FPGA en 16 8-bis NAND flash
toestelle, ontwerp en gebou. Fisiese metings was ’n sukses. ’n Skryftempo van 12 MB/s
is gehaal, tesame met die korrekte werking van die ander hooffunksies.
| Identifer | oai:union.ndltd.org:netd.ac.za/oai:union.ndltd.org:sun/oai:scholar.sun.ac.za:10019.1/50474 |
| Date | 04 1900 |
| Creators | Horsburgh, Ian J. |
| Contributors | Bakkes, P. J., Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering. |
| Publisher | Stellenbosch : Stellenbosch University |
| Source Sets | South African National ETD Portal |
| Language | en_ZA |
| Detected Language | English |
| Type | Thesis |
| Format | 127 p. : ill. |
| Rights | Stellenbosch University |
Page generated in 0.0275 seconds