¡@¡@A single chip of variable length FFT processor is presented in this thesis. This processor can be applied for the applications with 128/256/512/1024/2048-point FFT. This processor is based on SDF (single path delay feedback) pipeline architecture with radix-2^3 computation element. The number of bits for input data and twiddle factors is carefully selected by system simulation to meet the requirements of OFDM system. In addition, we propose a feedback twiddle factor generator to instead the lookup table for twiddle factors to reduce the storage size of memory.
The FFT processor is carried out by CMOS 0.35£gm 2P4M process with core area 3.381x3.3625 mm^2. In the gate level simulation, the output data rate of this FFT processor is above 22.72MHz, so the processor can meet the requirement of IEEE 802.16e standard.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0215107-012450 |
| Date | 15 February 2007 |
| Creators | Liang, Wen-ko |
| Contributors | Ju-ya Chen, none, none, none, none |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0215107-012450 |
| Rights | not_available, Copyright information available at source archive |
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