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Implementation of Fading Channel Simulator

A Rayleigh/Rician fading channel based on Jakes¡¦ model is implemented by FPGA hardware in this thesis. Parameters, including vehicular speed, carrier frequency, quantization bits and internal clock rate, are carefully chosen according to the fading statistics. Verification of this fading channel hardware is carried out on Altera FPGA board with functional and time sequential test. Finally, performance of a differential PSK modem via fading and noisy channel is simulated and emulated in both software and hardware methods.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0828103-163403
Date28 August 2003
CreatorsWu, Yang-Ying
ContributorsKen-Huang Lin, Ching-Piao Hung, Ju-Ya Chen, Jieh-Chian Wu
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0828103-163403
Rightsrestricted, Copyright information available at source archive

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