This dissertation presents circuit techniques for designing high performance amplifiers. In low power design, the range of common mode input signal shrinks due to reduced power supply voltage. In addition, due to reduced bias current, noise density rises. The reduced input signal range and raised noise floor severely degrade system dynamic range. A novel rail to rail input circuit is presented. The proposed circuit has advantages over conventional circuits in term of noise and power consumption. Moreover, due to reduced bias current, low power amplifiers typically have lower bandwidth and slew rate, which limits their dynamic performance. The bandwidth is further reduced at high gain settings because of the constant gain bandwidth product. A novel self-adaptive compensation technique to extend small signal bandwidth and improve slew behavior is presented. If an amplifier needs to drive various capacitive and/or resistive loads, parallel Miller compensation is the most power efficient frequency compensation scheme. However, the frequency response of parallel Miller compensation is complicated and no thorough analysis on frequency response has been given in literatures. To illustrate the connection between poles/zeros and each individual circuit component, we use a design oriented approach to derive transfer functions for various load conditions. With these transfer functions, circuit designers can optimize their design accordingly. As a case study, a low power precision instrumentation amplifier is designed. Compared to low power instrumentation amplifiers on the market or reported in literature, it can save at least 40% power, meanwhile offer higher bandwidth and faster slew rate at typical gain settings. Many challenges also exist in designing high voltage amplifiers. To achieve low cost and high performance, a novel topology of a high voltage current sensing amplifier is proposed. With this topology, major portion of amplifiers can be designed with low voltage, for instance, 5 V, devices, and only a limited amount of LDMOS are required to stand off high voltage. This topology does not have high noise gain as conventional solutions have. The same principle can be used for other high voltage amplifiers. A prototype chip is fabricated. The amplifier functions as expected. Test results are presented.
| Identifer | oai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/294044 |
| Date | January 2013 |
| Creators | Wan, Quan |
| Contributors | Hariri, Salim A., Marcellin, Michael W., Akoglu, Ali, Hariri, Salim A. |
| Publisher | The University of Arizona. |
| Source Sets | University of Arizona |
| Language | English |
| Detected Language | English |
| Type | text, Electronic Dissertation |
| Rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. |
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