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FORMAL: A SEQUENTIAL ATPG-BASED BOUNDED MODEL CHECKING SYSTEM FOR VLSI CIRCUITS

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Identiferoai:union.ndltd.org:OhioLink/oai:etd.ohiolink.edu:case1144614543
Date10 April 2006
CreatorsQiang, Qiang
PublisherCase Western Reserve University School of Graduate Studies / OhioLINK
Source SetsOhiolink ETDs
LanguageEnglish
Detected LanguageEnglish
Typetext
Sourcehttp://rave.ohiolink.edu/etdc/view?acc_num=case1144614543
Rightsunrestricted, This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.

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