So far, only CMOS compatible and scalable hafnia-zirconia (HZO) based ferroelectric (FE) n-FeFETs have been reported. To enable the full ferroelectric hierarchy [1] both p- and n-type devices should be available. Here we report a p-FeFET with a large memory window (MW) for the first time. Moreover, we propose different integration schemes comprising structures with and without internal gate resulting in metal-FE-insulator-Si (MFIS) and metal-FE-metal-insulator-Si (MFMIS) devices which could be used to tackle the problem of interface (IF) degradation and possibly decrease the power consumption of the devices.
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:77564 |
| Date | 25 January 2022 |
| Creators | Winkler, Felix, Pešić, Milan, Richter, Claudia, Hoffmann, Michael, Mikolajick, Michael, Bartha, Johann W. |
| Publisher | IEEE |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | info:eu-repo/semantics/acceptedVersion, doc-type:conferenceObject, info:eu-repo/semantics/conferenceObject, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | 978-1-72812-112-3, 10.1109/DRC46940.2019.9046463 |
Page generated in 0.0023 seconds