Field Programmable Gate Arrays (FPGAs) are a reconfigurable hardware platform which enable the acceleration of software code through the use of custom-hardware circuits. Complex systems combining processors with programmable logic require partitioning to decide which code segments to accelerate. This thesis provides tools to help determine which software code sections would most benefit from hardware acceleration.
A low-overhead profiling architecture, called LEAP, is proposed to attain real-time profiles of an FPGA-based processor. LEAP is designed to be extensible for a variety of profiling tasks, three of which are investigated and implemented to identify candidate software for acceleration. 1) Cycle profiling determines the most time-consuming functions to maximize speedup. 2) Cache stall profiling detects memory-intensive code; large memory overheads reduce the benefits of acceleration. 3) Energy consumption profiling detects energy-inefficient code through the use of an instruction-level power database to minimize the system's energy consumption.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/29464 |
| Date | 11 August 2011 |
| Creators | Aldham, Mark |
| Contributors | Anderson, Jason, Brown, Stephen |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
Page generated in 0.0017 seconds