A hardware implementation can bring orders of magnitude improvements in performance
and energy consumption over a software implementation. Hardware design, however, can
be extremely difficult. High-level synthesis, the process of compiling software to hardware, promises to make hardware design easier. However, compiling an entire software
program to hardware can be inefficient.
This thesis proposes hardware/software co-design, where computationally intensive
functions are accelerated by hardware, while remaining program segments execute in
software. The work in this thesis builds a framework where user-designated software
functions are automatically compiled to hardware accelerators, which can execute serially or in parallel to work in tandem with a processor.
To support multiple parallel accelerators, new multi-ported cache designs are presented. These caches provide low-latency high-bandwidth data to further improve the
performance of accelerators. An extensive range of cache architectures are explored,
and results show that certain cache architectures significantly outperform others in a processor/accelerator system.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/33380 |
| Date | 21 November 2012 |
| Creators | Choi, Jongsok |
| Contributors | Brown, Stephen, Anderson, Jason |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
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