Power Hardware In Loop (PHIL) simulation is a test method where equipment intended for field application can be debugged and tested in the factory by connecting to a virtual power system model simulated on a real-time simulator. Hence the PHIL simulation may be very effective in developing, debugging and commissioning power equipment. However, due to imperfections (e.g., time delay, noise injection, phase lag, limited bandwidth) in the power interface, simulations in this method show errors or even instable results. This thesis presents means to improve the simulation accuracy of the PHIL simulation. In order to achieve this, a simulation model is constructed for the PHIL simulation process itself. Using simulation, the sensitivity of the simulation to parameters in the interface equipment as well as interface software is thoroughly investigated. One interesting result is that the simulation is significantly affected by phase delay. Based on the analysis, an improved algorithm that uses additional interface filters (implemented in hardware and/or software) is proposed. The thesis shows that more stable and accurate results can be obtained by using the new algorithm. The validity of the proposed methods is verified through a simulation based study and hardware based studies.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:MWU.1993/22050 |
| Date | 21 August 2013 |
| Creators | YOO, IL DO |
| Contributors | Gole, Aniruddha (Electrical Engineering), Annakkage, Udaya (Electrical Engineering) Rattanawangcharoen, Nipon (Civil Engineering) Ginn Ill, Herbert L.(Electrical Engineering, University of South Carolina) |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Detected Language | English |
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