Current Intel processors implement a variety of power saving features like frequency scaling and idle states. These mechanisms limit the power draw and thereby decrease the thermal dissipation of the processors. However, they also have an impact on the achievable performance. The various mechanisms significantly differ regarding the amount of power savings, the latency of mode changes, and the associated overhead. In this paper, we describe and closely examine the so-called software controlled clock modulation mechanism for different processor generations. We present results that imply that the available documentation is not always correct and describe when this feature can be used to improve energy efficiency. We additionally compare it against the more popular feature of dynamic voltage and frequency scaling and develop a model to decide which feature should be used to optimize inter-process synchronizations on Intel Haswell-EP processors.
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:30333 |
| Date | 24 October 2017 |
| Creators | Schöne, Robert, Ilsche, Thomas, Bielert, Mario, Molka, Daniel, Hackenberg, Daniel |
| Contributors | Technische Universität Dresden |
| Publisher | The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | doc-type:conferenceObject, info:eu-repo/semantics/conferenceObject, doc-type:Text |
| Source | Proceedings of E2SC 2016: 4th International Workshop on Energy Efficient Supercomputing. 14. November 2016, Salt Lake City. S. 69-76 ISBN 978-1-5090-3856-5 |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | 10.1109/E2SC.2016.015 |
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