Proliferation of non-linear, single-phase power electronics loads, such as personal computers, television sets, CFLs, has resulted in thousands of individual small harmonic current injectors connected to a distribution feeder network. Harmonic standard: IEC 1000-3-2 classifies such loads as Class D, “low-voltage” equipment with current emissions limited to 16A/Phase. Individual harmonic contributions of such loads appear insignificant; their collective contribution, however, is a matter of concern. The average order of voltage distortion usually varies between 4-6%; current distortion, however, is usually of the order of 100%. Limitations and high-costs associated with conventional harmonic mitigation measures, has furthered the need for regulation and alternative strategies. The objective of this research is to predict, and mitigate the effects of harmonic proliferation in the main supply current measured at the point of common coupling (PCC). An equivalent circuit model – an aggregation of single phase power electronics loads connected to the distribution feeder network is proposed as a part of a forward solution. Each load, individually, behaves as a harmonic current source; the proposed model combines these individual harmonic current injectors into a single harmonic source connected at the PCC and their collective contribution as a single composite harmonic signal. It represents harmonic conditions at the PCC and provides a theoretical measure of harmonic distortion in the supply current. Such a model finds application during harmonic compliance testing for single-phase power electronics loads; it simulates and predicts the harmonic response of such loads using a theoretical pure 60 Hz sine wave as the supply voltage diffcult to obtain physically, yet critical to such tests. The accuracy of the equivalent circuit model in predicting a harmonic response is pivotal to a successful forward solution. A feed-backwards mechanism is proposed. For a given harmonic supply voltage and circuit configuration of the equivalent circuit model, the feed-backwards method generates the modeled response and compares it to a reference physical response. Finally, it optimizes the circuit configuration to a unique Correction Factor that facilitates an accurate modeled response. Three optimization algorithms, labeled as Response Optimization algorithms have been developed to execute the feed-backwards mechanism. These algorithms are written in FORTRAN-90. / text
| Identifer | oai:union.ndltd.org:UTEXAS/oai:repositories.lib.utexas.edu:2152/7835 |
| Date | 21 June 2010 |
| Creators | Kapur, Virat |
| Source Sets | University of Texas |
| Language | English |
| Detected Language | English |
| Format | electronic |
| Rights | Copyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works. |
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