With the fast-approaching limits of single-threaded CPU performance, chip vendors are manufacturing an array of radically different computing architectures, including multicore and heterogeneous architectures, to continue to accelerate computer performance. An important emerging data point in the heterogeneous architecture design space is heterogeneity in instruction-set architecture (ISA). ISA-heterogeneity is emerging in many forms. An exemplar case is Smart I/O devices such as SmartNICs and SmartSSDs that incorporate CPUs of the RISC ISA family (e.g, ARM64, RISC-V), which when integrated with a highperformance server with CPUs of the CISC ISA family (e.g., x86-64) yields a single machine with heterogeneous-ISA CPUs. This thesis presents the design of a shared memory OS for a cache-coherent, shared memory heterogeneous-ISA hardware. The OS, called ZxOS, is built by modifying the open-source ZephyrOS, including its architecture-specific code and page mapping mechanism to create a memory region that can be shared across heterogeneous- ISA CPUs. Since existent heterogeneous-ISA hardware has physically discrete memory for ISA-heterogeneous CPUs, ZxOS targets a software emulation environment that emulates cache-coherent, shared memory heterogeneous-ISA hardware. Our experimental evaluation using a set of micro- and macro-benchmarks demonstrate ZxOS's functionality. In particular, they show that a multithreaded application's threads can be split across (simulated) ISA-heterogeneous cores for parallel execution and that thread's concurrent access of shared memory variables is consistent. / Master of Science / The computing industry saw a growing difficulty with power management and heat dissipation in single-core CPUs with high clock speeds. Chip vendors adapted multi-core chip strategy because it improved power and performance characteristics. This idea evolved into heterogeneous computing paradigm, which uses heterogeneous instruction-set-architecture(ISA) cores in a single system. Many server-grade specialized devices were provided with RISCbased general-purpose CPU to efficiently manage requests from the server. SmartNICs and SmartSSDs are the best examples of these smart devices. When integrated with generally present CISC(x86_64) processors in server space, these devices resulted in machine-level heterogeneous-ISA CPUs. This thesis presents a novel design of a shared memory OS for a cache-coherent, shared memory heterogeneous-ISA hardware. The OS, called ZxOS, is built by extending the ZephyrOS. Many of the architecture-specific codes were modified to create a memory region that can be shared across the cores. ZxOS is aimed at a software emulation environment for cache-coherent, shared memory heterogeneous-ISA systems. ZxOS has demonstrated the capability to run multi-threaded applications in a split fashion across heterogeneous-ISA cores. The heterogeneous-ISA cores execute threads parallelly, and the thread's shared memory interactions were observed to be consistent.
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/109113 |
| Date | 04 March 2022 |
| Creators | Krishnakumar, Ashwin |
| Contributors | Electrical and Computer Engineering, Ravindran, Binoy, Chantem, Thidapat, Nikolaev, Ruslan |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Language | English |
| Detected Language | English |
| Type | Thesis |
| Format | ETD, application/pdf, application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
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