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Software Design of A Task-level High Level Synthesis Method

Along with the development of VLSI technology and the trend of system-on-chip design, traditional high-level synthesis can not deal with relatively complexity of system-on-chip design. In order to achieve optimal resource allocation, meet its performance and power requirements, and reduce its design time, we need a high-level synthesis software dealing system-level behavior. In consideration of system complexity, we have proposed a high-level synthesis method that synthesis for the task-level grains in a system behavior. This method performs efficient task-level resource allocation, task binding and task scheduling to reach a system design that meets the low performance and power requirements with low implementation cost. We utilize simulated annealing technique to achieve its overall system optimization. We designed and implemented the software design of the task-level high-level synthesis method. In this research, the design consists of three modules: the initial synthesis module, the heuristic movement module and the performance evaluation module. We will use the software to carry out the experiments of the task-level high-level synthesis method on application systems to verify its capability in designing systematic chips.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0907104-185350
Date07 September 2004
CreatorsJian, Jia-Dau
ContributorsChia-Hsiung Kao, Chih-Chien Chen, Tsung Lee
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907104-185350
Rightsunrestricted, Copyright information available at source archive

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