A test-bench is created that injects digital pulses that emulate ATLAS LAr Front End Board electronic signal pulses in order to test prototypes. The prototypes are for new electronics for an upgrade to the CERN Large Hadron Collider that increases the rate of proton-proton collisions by an order of magnitude. This High-Luminosity Large Hadron Collider requires a completely new Trigger and Data Acquisition system to deal with information from detectors.
One such system that is currently being developed is the Liquid Argon Signal Processor (LASP) whose architecture is based on Field Programmable Gate Arrays (FPGA). Validation of individual modules of the LASP are of key importance in the development cycle. Additionally, verification of module behaviour with real ATLAS pulses will not be available until much later in the project timeline.
The injector project is implemented on an Intel Stratix 10 FPGA, using a soft-core NIOS II processor for TCP/IP communication with a workstation in order to transfer Monte Carlo simulation pulses to the FPGA, where it is then stored in a 2 GB DDR3 external memory. The pulses are then retrieved into internal memory buffers and are transmitted to the LASP at 40 MHz. The user is in complete control of the data pulses injected which is a vital property that would test LASP behaviour for different cases and possible failure modes. / Graduate
| Identifer | oai:union.ndltd.org:uvic.ca/oai:dspace.library.uvic.ca:1828/12082 |
| Date | 31 August 2020 |
| Creators | Shroff, Maheyer Jamshed |
| Contributors | McPherson, Robert A., Keeler, Richard K. |
| Source Sets | University of Victoria |
| Language | English, English |
| Detected Language | English |
| Type | Thesis |
| Format | application/pdf |
| Rights | Available to the World Wide Web |
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