Design and evaluation of a technology-scalable architecture for instruction-level parallelism

Description

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Links & Downloads

1. http://www.lib.utexas.edu/etd/d/2007/nagarajanr54359/nagarajanr54359.pdf#page=3

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Additional Fields

Identifer	oai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/191736114
Date	January 1900
Creators	Nagarajan, Ramadass,
Publisher	[Austin, Tex. : University of Texas Libraries,
Source Sets	OCLC
Language	English
Detected Language	English