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Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors / Konstruktion och utvärdering av kompakta 5T SRAM cache för avancerade mikroprocessorer

<p>This thesis presents a five-transistor SRAM intended for the advanced microprocessor cache market. The goal is to reduce the area of the cache memory array while maintaining competitive performance. Various existing technologies are briefly discussed with their strengths and weaknesses. The design metrics for the five-transistor cell are discussed in detail and performance and stability are evaluated. Finally a comparison is done between a 128Kb memory of an existing six-transistor technology and the proposed technology. The comparisons include area, performance and stability of the memories. It is shown that the area of the memory array can be reduced by 23% while maintaining comparable performance. The new cell also has 43% lower total leakage current. As a trade-off for these advantages some of the stability margin is lost but the cell is still stable in all process corners. The performance and stability has been validated through post-layout simulations using Cadence Spectre.</p>

Identiferoai:union.ndltd.org:UPSALLA/oai:DiVA.org:liu-2286
Date January 2004
CreatorsCarlson, Ingvar
PublisherLinköping University, Department of Electrical Engineering, Institutionen för systemteknik
Source SetsDiVA Archive at Upsalla University
LanguageEnglish
Detected LanguageEnglish
TypeStudent thesis, text
RelationLiTH-ISY-Ex, ; 3481

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