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Design and Analysis of High-Speed Arithmetic Components

In this dissertation, the design and analysis of several fast arithmetic components are presented. Our contributions focus on the fast CORDIC rotation architectures and multipliers. In the CORDIC design, we proposed a fast rotation architecture that can reduce by half the average number of rotations. Furthermore, a new parallel CORDIC rotation algorithm and architecture (called para-CORDIC) is proposed that leads to smaller area and delay compared with the conventional CORDIC algorithm and previous works. In the design of the multiplier generator, a delay-efficient algorithm is used to perform the partial products summation and the final addition during the synthesis of fast parallel multipliers based on standard cell library or other full-custom circuit components. In the field of fixed-width multiplier designs, a lower-error fixed-width carry-free multiplier with low-cost compensation circuits is proposed that has smaller absolute average errors and variances compared with pervious methods.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-1211104-165009
Date11 December 2004
CreatorsJuang, Tso-Bing
ContributorsTien-fu Chen, Bin-da Liu, Shen-fu Hsiao, Jiun-in Guo, Chua-chin Wang, Ing-jer Huang
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageEnglish
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1211104-165009
Rightsnot_available, Copyright information available at source archive

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