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Prostředí pro verifikaci digitálních filtrů / Software for digital filter verification

Diploma thesis deals with design of verification environment for analyzing systems with digital filters. Verification environment is written in SystemVerilog language and it is generated by program, which is also providing generation of input data for system of filters. Matlab environment is used for gaining the reference data. The simulation of the designed involvement with digital filters is performed by program ModelSim. The most watched parameter is functional coverage which indicates how big part of the HDL description has been tested.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:242188
Date January 2016
CreatorsTesařík, Jan
ContributorsDvořák, Vojtěch, Pristach, Marián
PublisherVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

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