The increasing use of the internet demands more powerful routers with higher
speed, less power consumption and less physical space occupation. IP lookup
operation is one of the major concerns in today&rsquo / s routers for providing such
attributes. To accomplish IP lookup on routers, hardware or software based
solutions can be used. In this thesis, an SRAM based pipelined architecture
proposed earlier for ASIC implementation is re-designed and implemented on an
FPGA in the form of a BRAM based pipelined 8x8 torus architecture using Xilinx
ISE and simulated and verified using Modelsim Simulator. Some necessary
modifications and improvements for FPGA implementation are carried out. The
results of our experiments, which are performed for a real router lookup table and a
real time traffic load with various optimizations, are also presented. Our study and
design effort demonstrates the feasibility of the FPGA implementation of the
proposed technique, of course with a considerable performance penalty.
| Identifer | oai:union.ndltd.org:METU/oai:etd.lib.metu.edu.tr:http://etd.lib.metu.edu.tr/upload/12614192/index.pdf |
| Date | 01 February 2012 |
| Creators | Ozkaner, Akin |
| Contributors | Bazlamacci, Cuneyt F. |
| Publisher | METU |
| Source Sets | Middle East Technical Univ. |
| Language | English |
| Detected Language | English |
| Type | M.S. Thesis |
| Format | text/pdf |
| Rights | To liberate the content for public access |
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