Three-dimensional integrated circuits (3D-IC) have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs while also helping to reduce wire delay and increase memory throughput. While this technology offers many potential advantages, it also produces large thermal mismatch stress in 3D-IC structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via diameter and layout geometry. TSV-induced stress effects on electron/hole mobility and device performance will be studied for the widely used 6-transistor (6T) SRAM cell. Simulation results in this study show that static noise margin (SNM), Read Margin (RM) and write margin (WM) tend to increase with decreasing electron mobility or increasing hole mobility. Considering TSV-induced stress, we propose that for practical layouts of TSV-based 3D-IC, p-type substrates should be placed further away from TSVs or closer to the smaller TSVs if multiple TSVs exist. / text
| Identifer | oai:union.ndltd.org:UTEXAS/oai:repositories.lib.utexas.edu:2152/ETD-UT-2012-08-6222 |
| Date | 30 October 2012 |
| Creators | Zhang, Wen, 1990- |
| Source Sets | University of Texas |
| Language | English |
| Detected Language | English |
| Type | thesis |
| Format | application/pdf |
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