SOC (System-On-Chip) designs are more and more popular, concurrently, more and more new challenges system integrators will meet. One out of these challenges is testing problem. Our research is focus on how to testing and debugging the microprocessor cores that embedded in an SOC. Not only test the microprocessor cores but also test the interconnecting wire among these embedded microprocessor cores. This thesis explores architectural alternatives in the integration of embedded in-circuit emulation (ICE) into an SOC chip with multiple micro-controller/processor cores. The alternatives include distributed, centralized and hierarchical styles. Advantages and disadvantages of these alternatives are analyzed.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0821100-150631 |
| Date | 21 August 2000 |
| Creators | Kao, Chung-Fu |
| Contributors | Ing-Jer Huang, Chung-Ho Chen, Min-hon Jing, Juinn-Dar Huang, James Kuo |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0821100-150631 |
| Rights | unrestricted, Copyright information available at source archive |
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