Modern system-on-chip consists of an increasing number of highly complex modules. The quality of the interfaces and throughput of communication connections between these components are crucial to the performance of the system, since communication is often the main bottleneck in modern application domains like multimedia.
In this thesis, a bus-based communication architecture synthesis approach is proposed. Given the result of hardware/software partitioning and pipelined scheduling, the proposed approach constructs a communication topology which meets the constraints. We begin with the minimum number of AHB and an APB, each time we add an AHB and do some transformation such as merging or setting local buses. Our goal is to find the bus architecture which has minimum area. We use integer programming to construct a bus architecture each time, until the bus architecture with the minimum area are found. By this approach, we can save a lot of time required to design the communication architecture manually.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0801105-100013 |
| Date | 01 August 2005 |
| Creators | Liao, Ren-Zheng |
| Contributors | Pei-yin Chen, Yun-nan Chang, Jer-min Jou, Shen-fu Siao, Shiann-rong Kuang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801105-100013 |
| Rights | not_available, Copyright information available at source archive |
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