Major challenges in maintaining quality and reliability in today’s microelectronics devices come from the ever increasing level of integration in the device fabrication, as well as the high level of current densities that are carried through the microchip during operation. In order to have a framework for design and reliability assessment, it is imperative to develop a predictive capability for the thermal response of micro-electronic components. A computationally efficient and accurate multi-scale transient thermal methodology was developed using a combination of two different approaches: “Progressive Zoom-in” method and “Proper Orthogonal Decomposition (POD)” technique. The proposed technique has the capability of handling several decades of length scale from tens of millimeter at “package” level to several nanometers at “interconnects” level at a considerably lower computational cost, while maintaining satisfactory accuracy. This ability also applies for time scales from seconds to microseconds corresponding to various transient thermal events. The proposed method also provides the ability to rapidly predict thermal responses under different power input patterns, based on only a few representative detailed simulations, without compromising the desired spatial and temporal resolutions. It is demonstrated that utilizing the proposed model, the computational time is reduced by at least two orders of magnitude at every step of modeling.
Additionally, a novel experimental platform was developed to evaluate rapid transient Joule heating in embedded nanoscale metallic films representing buried on-chip interconnects that are not directly accessible. Utilizing the state-of-the-art sub-micron embedded resistance thermometry the effect of rapid transient power input profiles with different amplitudes and frequencies were studied. It is also demonstrated that a spatial resolution of 6 µm and thermal time constant of below 1 µs can be achieved using this technique. Ultimately, the size effects on the thermal and material properties of embedded metallic films were studied. A state-of-the-art technique to extract thermal conductivity of embedded nanoscale interconnects was developed. The proposed structure is the first device that has enabled the conductivity measurement of embedded metallic films on a substrate. It accounts for the effect of the substrate and interface without compromising the sensitivity of the device to the thermal conductivity of the metallic film. Another advantage of the proposed technique is that it can be integrated within the structure and be used for measurements of embedded or buried structures such as nanoscale on chip interconnects, without requiring extensive micro-fabrication. The dependence of the thermal conductivity on temperature was also investigated. The experimentally measured values for thermal conductivity and its dependence on temperature agree well with previous studies on free-standing nanoscale metallic bridges.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/51786 |
| Date | 22 May 2014 |
| Creators | Barabadi, Banafsheh |
| Contributors | Joshi, Yogendra K., Kumar, Satish, Graham, Samuel, Swaminathan, Madhavan, Bakir, Muhannad, Sukharev, Valeriy |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Language | en_US |
| Detected Language | English |
| Type | Dissertation |
| Format | application/pdf |
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