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Passivity checking and enforcement in VLSI model reduction exercise

Thesis (M. Phil.)--University of Hong Kong, 2008. / Includes bibliographical references (leaf 95-101) Also available in print.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/296934007
Date January 2008
CreatorsLiu, Yansong.
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceClick to view the E-thesis via HKUTO

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