Rapid advancement and innovation in semiconductor research have continuously helped in designing efficient and complex integrated circuits in miniature size. As the device technology, is aggressively scaling to improve the device performance, the issues related to device interconnects, power, and reliability have become a major concern for the designers. These challenges make the design and validation of ASIC extremely complicated.
The primary idea of this work is to develop automation tools, to be used in the physical design flows to improve the efficiency of the design flow. The first tool named as variation analysis tool automates the on-chip variation modeling used in the post-layout timing closure phase in the physical design flows. The proposed variation analysis tool models three types of variations such as on-chip variation (OCV), advanced on-chip variation (AOCV) and parametric on-chip variation (POCV). The results of the proposed tool have compared with the Synopsys PrimeTime™ results, and the results show average around 98% accuracy compared to the PrimeTime™. The second tool is for automating repeater analysis in the physical design flows. The repeater automation tool can be used to automate the repeater or buffer insertion process, while technology process is changed from one to another. The tool can calculate the best possible repeater distance for any given metal layer and also, the number of repeaters, combinational or sequential for the user given distance and frequency. The accuracy of this script is compared with the repeater insertion based on the synthesis tools and also, the SPICE simulation.
| Identifer | oai:union.ndltd.org:pdx.edu/oai:pdxscholar.library.pdx.edu:open_access_etds-5627 |
| Date | 20 August 2018 |
| Creators | Mahalik, Subrat |
| Publisher | PDXScholar |
| Source Sets | Portland State University |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Dissertations and Theses |
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